Digital transceivers have been developed to transmit and receive signals according to a variety of protocols, such as SONET, SDH, 10 GbE, PCI Express, SATA, Fibre channel, or the like. As part of the validation process for a transceiver, the transceiver is subjected to a test pattern that has been modulated to include jitter. Jitter in a high-frequency digital signal is manifested by deviation in a characteristic of the pulses, such as amplitude, phase timing, or the width of the signal pulse. Jitter may be caused by electromagnetic interference (EMI) and/or crosstalk with other signals. An important characteristic of a receiver design is its jitter tolerance.
Sophisticated and costly test equipment have been developed to emulate various signal streams that a transceiver may be expected to encounter in actual use, including “stressed” signal streams that have been modulated to include jitter. Unfortunately, the costs of automated test equipment (ATE) and the complexity of integrated circuits are both rising quickly.